FIG. 10 is a diagram illustrating a prior art memory control system disclosed in Japanese Published Patent Application Hei.1-169557. In the figure, reference numerals 101a.about.101d designate CPUs which perform operation processing or the like according to a prescribed procedure described as a program. Reference numerals 104 and 105 designate memories storing data or the like which are processed by the CPUs 101a.about.101d. Reference numeral 102 designates a memory controller controlling the memories 104 and 105. Reference numeral 103 designates a duplex writing device provided in the memory controller 102 to control the duplex writing.
This apparatus includes sixteen clusters, i.e., cluster 0.about.cluster 15, and each cluster includes four CPUs and two memories owned jointly.
A description is given of the operation. When an instruction ordered by a CPU instructs duplex writing for writing the same information into two memories at the same time, one of the CPU 101a.about.101d outputs a request for duplex writing to the duplex writing device 103 in the memory controller 102. When the duplex writing device 103 receives the duplex writing request signal, it produced a designated writing address for the memory device 104 as well as a corresponding duplex writing address for the other memory 105, and sends writing requests to the memories 104 and 105 at the same time. Accordingly, the information to be stored in the memory device can be stored in the two memories by one time writing operation.
FIG. 11 is a diagram for explaining a prior art system for controlling data transfer to a duplex memory system disclosed in Japanese Published Patent Application Hei. 3-144739. In the figure, reference numerals 201 and 204 designate CPUs performing operation processing or the like according to a prescribed procedure described as a program. Reference numerals 202 and 205 designate memories storing data or the like which are processed by the CPUs 201 and 204. Reference numerals 203 and 209 designate inter-system information transfer device for transferring information between two systems of CPU partitioned by one dot chain line in the figure. Reference numeral 206 designates a data bus for communicating data through the CPU 201, the memory 202, and the inter-system information transfer device 203. Reference numeral 207 designates a data bus for communicating data through the CPU 204, the memory 205, and the inter-system information transfer device 209. Reference numeral 208 designates an inter-system information transmitting circuit in the inter-system information transfer device 203. Reference numeral 212 designates an inter-system data bus communicating data between the inter-system information transfer devices 203 and 209. Reference numeral 210 designates a buffer circuit into which data sent out from the inter-system information transmitting circuit 208 through the inter-system data bus 212 is written. Reference numeral 211 designates a writing information transmitting circuit for writing information from the CPU 201 in an active state system (hereinafter referred to as ACT system) to the memory 205 of the CPU 204 in an non-active state system (hereinafter referred to as STBY system). Reference numeral 213 designates a data comparing circuit for comparing the data read out from the ACT system with information read out from the STBY system.
A description is given of the operation.
When a data writing access to the ACT system memory 202 is generated from the ACT system central processing unit 201, a memory address, data to be written in, and a writing signal are communicated to the memory 202 via the data bus 206, and also communicated to the inter-system information transfer device 203 and are latched inside the inter-system information transmitting circuit 208. These signals are also communicated to the STBY system inter-system information transfer device 209 via the inter-system data bus 212 and are written in into the buffer circuit 210 synchronized with ACT system clocks. These signals are read out from the buffer circuit 210 independently from the operation of the ACT system data bus but synchronized with the STBY system clocks, and are sent out to the data bus 207 via the writing information transmitting circuit 211 to be written in into the STBY system memory 205.
When a data reading access to the ACT system memory 202 is generated from the ACT system central processing unit 201, a memory address and a reading signal are transferred to the memory 202 via the data bus 206, also communicated to the inter-system information transfer device 203, and they are latched inside the inter-system information transmitting circuit 208. The memory 202 communicates the data that is read out from the memory address received, of the memory to the central processing unit 201 via the data bus 206 as well as communicates the same to the inter-system information transfer device 203, and they are latched inside the inter-system information transmitting circuit 208. These signals are also communicated to the inter-system information transfer device 209 via the inter-system data bus 212, and are written into the buffer circuit 210 synchronized with ACT system clocks. These signals are read out from the buffer circuit 210 independent on the operation of the ACT system data bus but synchronized with STBY system clocks, the read out data are latched inside the data comparing circuit 213. The memory address and the read out signal are output to the data bus 207 via the data comparing circuit 213 and are input to the memory 205. Because the access is reading out access, the read out data from the memory 205 in the STBY system are output to the data bus 207, and are latched inside the data comparing circuit 213. The ACT system read out data and the STBY system read out data are compared by the data comparing circuit 213, and when there is incoincidence, an interrupting notice is output to the ACT system CPU.
FIG. 12 is a diagram illustrating a prior art multi-processor system. In the figure, reference numerals 301a and 301b designate central processing units which perform operation processing or the like in accordance with a prescribed procedure described as a program. Reference numerals 302a and 302b designate memories storing data or the like processed by the CPU 301a and 301b, respectively. Reference numeral 303 designates a CPU bus connecting the CPU 301a and 301b via the bus gates 305a and 305b. Reference numeral 304 designates a bus arbiter for arbitrating the occupation of the CPU bus 303 by performing open/close control of the bus gates 305a and 305b. Reference numerals 305a and 305b designate bus gates which transmit or do not transmit the I/O (input/output) data of the CPUs 301a and 301b, respectively to the CPU bus 303. Reference numerals 306a and 306b designate address decoders for decoding the output data of the CPUs 301a and 301b, respectively, and transmitting those to the bus arbiter 304. Reference numerals 307a and 307b designate memory access request signals which are output from the address decoders 306a and 306b, respectively. Reference numeral 308a and 308b designate bus gate control signals which are output from the bus arbiter 304.
A description is given of the operation.
When the CPU 301a accesses the memory 302a or 302b, the CPU 301a outputs an address for the memory 302a or 302b. The address decoder 306a decodes the address and outputs a memory access request signal 307a to the bus arbiter 304. Then, the bus arbiter 304 allows the CPU 301a to access a memory and outputs a bus gate control signal 308a unless the other CPU 301b is in access to the memory 302a or 302b, i.e., unless the address decoder 306b is outputting a memory access request signal 307b to the bus arbiter 304, whereby the bus gate 305a is opened to make the CPU bus 303 opened to the CPU 301a. To the contrary, when the CPU 301b has already accessed the memory 302a or 302b, the bus arbiter 304 does not allow the CPU 301a to access a memory and outputs the bus gate control signal 308a after the access by the CPU 301b is completed.
The memory control system in the prior art information processing apparatus is performed as described above, and the duplex writing device has to produce a duplex writing address also for the other memory, corresponding to the writing address of the designated memory. Further, CPU buses of the same number as that of the memories are required, increasing the hardware quantity.
In the data transfer control system for transferring data to the duplex memory in the prior art information processing apparatus described above, the memory content read out from the STBY system memory is only used when it is compared with the memory content of the ACT system memory that is temporarily stored in the buffer circuit, and it is impossible for the ACT system CPU to arbitrarily read out the memory content of the STBY system memory. In addition, because the data transfer control system uses a buffer, the memory writing in the other system takes a longer time than that in the self system, and the identity of the memory content is not secured during the delayed time between the two systems, thereby causing a malfunction.
Further, in the multi processor system in the prior art information processing apparatus constructed described above, while one side CPU is in access to a memory, the other side CPU is obliged to wait for an access unconditionally, whereby processing ability per unit time is reduced.